FIG. 1 shows simplified plot 20 of transmission line pulse current (I) versus voltage (V) for a typical electrostatic discharge (ESD) protection device. As the applied voltage is increased, very little current flows until triggering voltage 21 is reached at voltage Vt1. Once triggered into operation, the ESD device conducts and the current increases to holding point 22 with current Ih and voltage Vh. Depending upon the internal impedance of the voltage source, current and voltage may further increase to point 23 at current It2 and voltage Vt2, beyond which destructive failure may occur leading to further current increase accompanied by voltage decrease. Electrostatic discharge (ESD) protection devices are intended to remain quiescent during normal operation of an associated semiconductor (SC) device(s) or non-SC device(s) or integrated circuit (IC), i.e., the “protected element(s)”, having a normal operating voltage Vo, but turn on when excessive voltage arises, thereby preventing damage to the protected element(s). The triggering voltage Vt1 of the ESD device should exceed the maximum normal DC operating voltage Vo(MAX) of the protected elements, otherwise the ESD device will interfere with normal operation of the protected elements. Further, Vt1 should be less than, for example, a voltage VTR (usually a transient voltage) large enough to damage the protected element(s), hereafter referred to as the protected element break-down voltage, abbreviated as VTR(PEBD). Thus, the ESD device should be designed so that Vo(MAX)<Vt1<VTR(PEBD).
One of the difficulties of using bipolar transistors for ESD devices is that their turn-on voltages Vt1 for DC operation (i.e., Vt1DC) and transient operation (i.e., Vt1TR) are often different, i.e., Vt1DC is not equal to Vt1TR. This has the consequence of reducing the margin between the maximum DC operating voltage that can be applied to the circuit in normal operation without triggering the ESD device and the transient ESD voltage that can trigger the ESD device into operation to provide protection against excessive voltage. It is desirable to have the DC and transient trigger voltages of the ESD device be as nearly equal as possible. However, with current day devices, this is often difficult or impossible to achieve.
Thus, a need continues to exist for improved structures and methods for ESD protection devices in which the voltage margin of the ESD structures is improved by decreasing the difference (ΔV=|Vt1TR−Vt1DC|) between the transient ESD turn-on voltage Vt1TR and DC ESD turn-on voltage Vt1DC. This improvement has a further desirable consequence of improving the tolerance of the ESD protection devices to random process variations that can occur during SC device and/or IC manufacture, which might otherwise shift the DC ESD turn-on voltage Vt1DC below the maximum DC operating voltage of the protected element(s) Vo(MAX) or increase the transient ESD turn-on voltage Vt1TR above the maximum (no-damage) voltage tolerance of the protected element(s) VTR(PEBD). Either of such conditions can cause rejection of the finished devices, thereby lowering overall manufacturing yield and increasing overall manufacturing cost.